Bit timing is the count of time Quanta(tq,a basic unit of bit time) required to carry a single bit(i.e tour of a bit on CAN bus from writing to reading) on CAN Bus.reciprocal of Bit timing is known as Bit rate or Nominal bit rate.
As per CAN standard CAN supports bit-rate up to 1000 kbps. it all depends on the CAN network length.bit rate can be configured individually for each CAN node connected on CAN network.
The oscillator frequencies of Nodes(ECUs) have some instability because of some environmental factors which can cause synchronization error but every Node is configured itself to maintain its bit synchronization by adjusting bit time if the frequency deviation is within its tolerance limit.
Keeping the attention at bit synchronization a bit time is divided into 4 segments and each segment has some specific programmable number of time quanta(tq) –
Nominal Bit Time = Tsync_seg+TSEG1+TSEG2
Where,
TSEG1 =Tprop_seg+Tphase_seg1
TSEG2 =Tphase_seg2
Tsync_seg=1 Tq
TSEG1 ,TSEG2 = N*tq(i.e integral multiple of tq)
See the table for allowed values for each segment:
| Segments | Values | Description |
|---|---|---|
| Tsync_seg | 1 tq | Fixed |
| Tprop_seg | [1..8] tq | Programmable.(Adjust according to physical delay time) |
| Tphase_seg1 | [1..8] tq | Programmable.(Lengthened temporarily for synchronization) |
| Tphase_seg2 | [1..8] tq | Programmable.(Shortened temporarily for synchronization) |
Time Quanta(Tq)
Time quanta(tq) is the basic unit of the bit time and its formula is –
tq=BRP/fsys
BRP=Baud Rate Prescaler
fsys =MCU system Clock(typically =Fosc)
Synchronization Segment
It is the first part of the bit time of fix length 1tq which Indicates the start of bit transmission. This segment is used to synchronize the transmission between nodes.
If Bit transition occurs after Tsync_seg then it is known as Positive phase error and this error will compensate by lengthening the Tphase_seg1.
If Bit transition occurs before Tsync_seg then it is known as Negative phase error and this error will compensate by shortening the Tphase_seg2.
for detail study about the Segments and bit timing, you can read the paper by Florian Hartwich and Armin Bassemir by Robert Bosch: CAN Bit Timing.
Q. Calculate Required Time Quanta to achieve 500kbps baud rate if the system clock is 40mhz and CAN clock divider is 4.
CAN clock(fcan)=40/4=10mhz
time Quanta(tq)=1/fcan=1/10=100ns
bit rate =500kbps
bit time=1/500kbps=2us
no of tq=2us/100ns=20tq.
Q. Configure TSEG1 and TSEG2 to set sampling at 80% of a bit time.
(Tsync_seg+TSEG1)/(Tsync_seg+TSEG1+TSEG2)=80%
as we calculated above: bit time = Tsync_seg+TSEG1+TSEG2=20tq
so , (1+TSEG1)/(20)=80%
TSEG1=16-1=15
so TSEG2=20-1-15=4
so final values are :
|
1 2 3 4 5 |
Tsync_seg=1(fixed) TSEG1=15 TSEG2=4 |